In the block diagram 100 of a prior art registered memory module 120 as shown in FIG. 1, the memory register 122 buffers signals from the memory controller 110 to the dynamic random access memory (DRAM) 126. By buffering the signals from the memory controller 110, the electrical loading on the memory controller 110 is reduced and it increases the reliability of high-speed data access to the DRAM 126.
The memory register 122 has a phase-locked loop (PLL) 124 that is driven by a pair of input differential clocks CLK 140 and CLK# 142 from the memory controller 110. The dynamic power consumption of the PLL 124 is relatively higher than the power consumption of the other components present in the registered memory module 120. In addition, when the PLL 124 is locking to the input differential clocks CLK 140 and CLK# 142 to generate the output differential clocks CLK 150 and CLK# 152, no write or read operation to the DRAM 126 can be performed until the PLL 124 is locked.